1. Field of the Invention
The present invention relates to a pattern data generation method and a design layout generating method, and more particularly, to a correction/verification process for gate patterns of transistors.
2. Description of the Related Art
In recent years, in a semiconductor integrated circuit, the formation of finer patterns of elements and wiring that compose the circuit has been promoted further. Along with that, there is a demand for a reduction in variations in the size of patterns. Particularly, when, in a process of forming gates of Metal-Insulator-Semiconductor (MIS) transistors, variations occur in the size thereof, the performance of the entire semiconductor integrated circuit is largely affected thereby.
Thus, fine patterns need to be accurately formed and an optical proximity correction (OPC) processing technique and a simulation technique for verifying correction results are necessary (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2006-53248).
Here, a verification simulation is performed for checking, when mask patterns that are corrected by the OPC process are transferred onto a wafer, what shape the transferred patterns will take. By this, it is verified that the patterns obtained by simulation match desired patterns.
In addition, when taking into account variations resulting from a process in, for example, the focal location or irradiated light exposure of an exposure apparatus used in a lithography process, it is checked whether all patterns fall within a set size range (hereinafter, referred to as the size spec).
In a verification simulation performed so far, the size spec is determined according to, for example, a difference in pattern size, gate, and wiring and normally the same size spec is applied to gate lengths of the same size. However, in a design layout, the setting range of the size spec is defined by a small range, regardless of the type of transistor.
On the other hand, along with the formation of finer patterns, margin of variations resulting from a process is reduced. Therefore, it tends to become difficult to compensate for a strict size spec that is common for all gate patterns.